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Design and Implementation of Carry Select Adder based On Wallace tree Multiplier using Adiabatic Logic
Abstract
The Wallace tree multiplier construction using a carry select adder (CSA) and this paper discusses adiabatic
logic. The proposed design aims to reduce power consumption while maintaining high performance.
Adiabatic logic is employed to reduce power dissipation by recycling energy during the logic transitions. The
Wallace tree multiplier is used to perform fast multiplication of two large numbers by breaking down the
multiplication process into smaller sub-tasks. The CSA is used as the adder to improve the performance of
the multiplier by reducing the propagation delay. The proposed design is simulated using a 90nm CMOS
process and the results show that the adiabatic Wallace tree multiplier using CSA achieves a significant
reduction in power consumption while maintaining high performance. This design is suitable for applications
that require high-speed multiplication with low power consumption, such as digital signal processing,
graphics processing, and cryptography.
Keywords
References
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DOI: https://doi.org/10.37591/jovdtt.v13i2.7540
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