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Survey on Built in Self-Test (BIST) for FPGA Application
Abstract
The integration of Field- Programmable Gate Arrays (FPGAs) in various applications has surged in recent years due to their flexibility and reconfigurability. However, ensuring the reliability and functionality of these FPGAs is a critical concern. Built-in Self-Test (BIST) techniques have emerged as a promising solution to address this challenge by providing on-chip testing capabilities. This survey explores the landscape of BIST methodologies specifically tailored for FPGA applications. The study delves into various BIST approaches, including deterministic and probabilistic techniques, highlighting their advantages, limitations, and suitability for different FPGA architectures. Additionally, the survey investigates the impact of BIST on area
overhead, power consumption, and test coverage.
Keywords
References
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DOI: https://doi.org/10.37591/jovdtt.v13i3.7827
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