Reduce the Leakage Current and Power in VLSI Technology

Abstract

Demand for portability Reduce and increase in size, low cost, low dynamic power, low leakage current, low sub threshold current, and the necessity to minimise at least one of these. Circuit complexity increases with circuit integration. Memory and microprocessors are included in mass-produced chips. Microcomputer systems central system memory uses dynamic random-access memory (DRAM). One benefit of DRAM memory is its high speed and capacity integration. The examination of DRAM memories with one and three transistors is presented in this research article. Three transistor DRAM implementations have the benefit of dynamic power dissipation reduction and recurrent precharge cycles. The quantity of DRAM activity, such as the possibility of random read/write operations, compact cell size in contrast to SRAM, incredibly unified, extremely low cost of production Often utilised as primary memory, Data stored is erratic; a cyclic refresh is required; speed is medium. DRAM is essentially a memory array with individual bit access; it can read and write data. These research articles also cover the DRAM's read, write, and hold capabilities as well as charge leakage and how it happens. To design and implement 1T and 3T DRAM, we employ Cadence Virtuoso Tool Design Systems, which simulates in an analogue design environment. The analysis of reducing low dynamic power is shown here.