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Reduce the Leakage Current and Power in VLSI Technology

Nisha Sharma, Laxmi Singh, Shilpa Tripathi

Abstract


Demand for portability Reduce and increase in size, low cost, low dynamic power, low leakage current, low sub threshold current, and the necessity to minimise at least one of these. Circuit complexity increases with circuit integration. Memory and microprocessors are included in mass-produced chips. Microcomputer systems central system memory uses dynamic random-access memory (DRAM). One benefit of DRAM memory is its high speed and capacity integration. The examination of DRAM memories with one and three transistors is presented in this research article. Three transistor DRAM implementations have the benefit of dynamic power dissipation reduction and recurrent precharge cycles. The quantity of DRAM activity, such as the possibility of random read/write operations, compact cell size in contrast to SRAM, incredibly unified, extremely low cost of production Often utilised as primary memory, Data stored is erratic; a cyclic refresh is required; speed is medium. DRAM is essentially a memory array with individual bit access; it can read and write data. These research articles also cover the DRAM's read, write, and hold capabilities as well as charge leakage and how it happens. To design and implement 1T and 3T DRAM, we employ Cadence Virtuoso Tool Design Systems, which simulates in an analogue design environment. The analysis of reducing low dynamic power is shown here.


Keywords


High performance, Low cost, Leakage Current, Low Power.

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References


Sung-Mo (Steve) Kang, Yusuf Leblebici, “CMOS Digital Integrated Circuits-Analysis and Design”, Third Edition Tata McGraw-Hill Edition, New Delhi, India.

G. Razavipour,A. Afzali-Kusha and M. Pedram, “Design and Analysis of Two Low-Power SRAM Cell Structures”,IEEE Transaction on VLSI systems,Vol. 17,No. 10,Oct. 2009,pp. 1551- 1555.

W. Zhao and Y. Cao, “New Generation of Predictive Technology Model for Sub-45nm Early Design Exploration,” IEEE Transactions on Electron Devices , vol. 53, no. 11, pp. 2816–2823, Nov. 2006.

Gasboro, J., and M. Horowitz, “A Single-Chip Functional Tester for VLSI Circuits,” 1990 ISSCC Digest of Technical Papers, pp 84-85.

Speck, D., “The Mosaic Fast 512K Scalable CMOS dRAM,” Proceedings of Conference on Advanced Research in VLSI, 1991, pp 229-244.

Hashimoto, M., K. Abe, and A. Seshadri, “An Embedded DRAM Module using a Dual Sense Amplifier Architecture in a Logic Process,” 1997 ISSCC

Digest of Technical Papers, pp 64-65.

1. Jing Tian , Bo Wu , and Zhongfeng Wang , Fellow, IEEE “High-Speed FPGA Implementation of SIKE Based on an Ultra-Low-Latency Modular Multiplier” IEEE Transactions On Circuits And Systems—I: Regular Papers, VOL. 68, NO. 9, September 2021.

Anirudh Raghunath, Shikha Bathla “Analysis and Comparison of Leakage Power Reduction Techniques for VLSI Design” International Conference on Computer Communication and Informatics (ICCCI -2021), Jan. 27-29, Coimbatore,INDIA 2021.

3. Shubham Sarkar, Hijal Chatterjee, Pritam Saha, Manoj Biswas “8-Bit ALU Design using m-GDI Technique”Proceedings of the Fourth International Conference on Trends in Electronics and Informatics (ICOEI 2020) IEEE Xplore Part Number: CFP20J32-ART; ISBN: 978-1-7281-5518-0,2020.

Sucharitha D,, Prudhvi Raj N, Sravya Reddy B , Sudheer Raja V “GDI Logic Based Design of Hamming-Code Encoder and Decoder for Error Free Data Communication” Proceedings of the Third International Conference on Computing Methodologies and Communication (ICCMC 2019) IEEE Xplore Part Number: CFP19K25-ART; ISBN: 978-1-5386-7808-4, 2019.


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