Open Access Open Access  Restricted Access Subscription or Fee Access

A Dual Material Control Gate Tunnel Field Effect Transistor for an Asymmetric Doping at Source and Drain Regions

Pratiksha Kharat


Double-Gate tunnel FET devices, which uses high-κ gate dielectric, are explored using realistic design parameters, showing an ON-current as high as 0.23 mA, a gate voltage of 1.8 V, an OFF-current of not more than 1 fA (neglecting gate leakage), an improved ordinary subthreshold swing of 57 mV/dec, and a lower point slope of 11 mV/dec. A dual material control gate tunnel field effect transistor for an asymmetric doping at source and drain regions is suggested. The gate consists of three segments with different work functions φ1, φ2, and φ3, which are named as tunnelling gate (M1), control gate (M2), and auxiliary gate (M3), individually. The 2-D nature of tunnel FET current flow is studied, which indicates that the current is not confined to a channel at the gate-dielectric surface. When temperature is varied, tunnel FETs with a high-κ gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of greater than 2×1011 is shown for simulated device with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is encouraging candidate to achieve better-than-ITRS low-standby-power switch activity.


Keywords: Band-to-band tunneling, double gate (DG), gated p-i-n diode, high-κ dielectric, subthreshold swing, tunnel field effect transistor (FET)

Cite this Article

Pratiksha Kharat. A Dual Material Control Gate Tunnel Field Effect Transistor for an Asymmetric Doping at Source and Drain Regions. Journal of VLSI Design Tools & Technology. 2018; 8(3): 45–53p.

Full Text:



Approach for ambipolar behaviour suppression in tunnel FET by work function engineering Kaushal Nigam, Pravin kondekar, Dheeraj Sharma, Accepted, n (23rd May 2016)

Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimization Eng-Huat Toh, Grace Huiqi Wang, Ganesh Samudra (published online 27 June 2007)

Gate Tunnel FET With High-κ Gate Dielectric Kathy Boucart and Adrian Mihai Ionescu, Member,IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 7, JULY 2007

J. Quinn, G. Kawamoto, and B. McCombe, “Subband spectroscopy by surface channel tunneling,” Surf. Sci., vol. 73, pp. 190–196, May 1978.

T. Baba, “Proposal for surface tunnel transistors,” Jpn. J. Appl. Phys., vol. 31, no. 4B, pp. L455–L457, Apr. 1992.

[6] W. Reddick and G. Amaratunga, “Silicon surface tunnel transistor,” Appl. Phys. Lett., vol. 67, no. 4, pp. 494–496, Jul. 1995.

J. Koga and A. Toriumi, “Three-terminal silicon surface junction tunneling device for room temperature operation,” IEEE Electron Device Lett., vol. 20, no. 10, pp. 529–531, Oct. 1999.

Steep Slope Devices: Enabling New Architectural Enabling Paradigms Karthik Swaminathan [email protected] DAC ’14 San Francisco, CA, USA Copyright 2014

Doping-less Tunnel Field Effect Transistor design & Approaches IEEE TRANSACTION ON NO. 10, October 2013

W. Hansch, C. Fink, J. Schulze, and I. Eisele, “A vertical MOS-gated Esaki tunneling transistor in silicon,” Thin Solid Films, vol. 369, no. 1/2, pp. 387–389, Jul. 2000.

C. Aydin, A. Zaslavsky, S. Luryi, S. Cristoloveanu, D. Mariolle, D. Fraboulet, and S. Deleonibus, “Lateral interband tunneling transistor in silicon-on-insulator,” Appl. Phys. Lett., vol. 84, no. 10, pp. 1780–1782, Mar. 2004.

J. Appenzeller, Y.-M. Lin, J. Knoch, and P. Avouris, “Band-to-band tunneling in carbon nanotube field-effect transistors,” Phys. Rev. Lett., vol. 93, no. 19, pp. 196805-1–196805-4, Nov. 2004.

P.-F. Wang, K. Hilsenbeck, T. Nirschl, M. Oswald, C. Stepper, M. Weis, D. Schmitt-Landsiedel, and W. Hansch, “Complementary tunneling transistor for low power application,” Solid State Electron., vol. 48, no. 12, pp. 2281–2286, Dec. 2004.

K. Bhuwalka, M. Born, M. Schindler, M. Schmidt, T. Sulima, and I. Eisele, “P-channel tunnel field-effect transistors down to sub-50 nm channel lengths,” Jpn. J. Appl. Phys., vol. 45, no. 4B, pp. 3106–3109, Apr. 2006.

K. Bhuwalka, J. Schulze, and I. Eisele, “Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering,” IEEE Trans. Electron Devices, vol. 52, no. 5, pp. 909–917, May 2005.

K. Bhuwalka, J. Schulze, and I. Eisele, “Performance enhancement of vertical tunnel field-effect transistor with SiGe in the delta p+ layer,” Jpn. J. Appl. Phys., vol. 43, no. 7A, pp. 4073–4078, 2004.

M. Born, K. Bhuwalka, M. Schindler, U. Abelein, M. Schmidt, T. Sulima, and I. Eisele, “Tunnel FET: A CMOS device for high temperature applications,” in Proc. 15th Int. Conf. Microelectron., 2006, pp. 124–127.

T. Nirschl, S. Henzler, J. Fischer, M. Fukle, A. Bargagli-Stoffi, M. Sterkel, Sedlmeir, C. Weber, R. Heinrich, U. Schaper, J. Einfeld, R. Neubert,U. Feklmann, K. Stahrenberg, E. Ruderer, G. Georgakos, A. Huber,

R. Kakoschke, W. Hansch, and D. Schmitt-Landsiedel, “Scaling properties of the tunneling field effect transistor (TFET): Device and circuit,” Solid State Electron., vol. 50, no. 1, pp. 44–51, Jan. 2006.

Q. Zhang, W. Zhao, and A. Seabaugh, “Analytic expression and approach for low subthreshold-swing tunnel transistors,” in Proc. DRC, Santa Barbara, CA, Jun. 20–22, 2005, pp. 161–162.

Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors (ITRS), 2005. [Online]. Available: http://

Guillaumot,X.Garros,F.Lime,K.Oshima,B.Tavel, A. Chroboczek, P. Masson, R. Truche, A. M. Papon, F. Martin,J. F. Damlencourt, S. Maitrejean, M. Rivoire, C. Leroux, S. Cristoloveanu, G. Ghibaudo, J. L. Autran, T. Skotnicki, and S. Deleonibus, “75 nm damascene metal gate and high-k integration for advanced CMOS devices,” in IEDM Tech. Dig., Dec. 8–10, 2002, pp. 355–358.

G. Hurkx, D. Klaassen, and M. Knuvers, “A new recombination model for device simulation including tunneling,” IEEE Trans. Electron Devices, vol. 39, no. 2, pp. 331–338, Feb. 1992.

Atlas User’s Manual, Silvaco Int., Santa Clara, CA, May 26, 2006.

K. Kim and J. Fossum, “Double-gate CMOS: Symmetrical- versus asymmetrical-gate devices,” IEEE Trans. Electron Devices, vol. 48, no. 2, pp. 294–299, Feb. 2001.

J. Knoch and J. Appenzeller, “A novel concept for field-effect transistors—The tunneling carbon nanotube FET,” in Proc. 63rd DRC, Jun. 20–22, 2005, vol. 1, pp. 153–156.

K. Boucart and A. M. Ionescu, “Double gate tunnel FET with ultrathin silicon body and high-k gate dielectric,” in Proc. ESSDERC, 2006, pp. 383–386.

F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, “Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance,” IEEE Electron Device Lett., vol. EDL-8, no. 9, pp. 410–412, Sep. 1987.

J. McPherson, J.-Y. Kim, A. Shanware, and H. Mogul, “Thermochemical description of dielectric breakdown in high dielectric constant materials,” Appl. Phys. Lett., vol. 82, no. 13, pp. 2121–2123, Mar. 2003.

24) Kathy Boucart received the B.S. degree in the subject of Radio/TV/Film from the Northwestern University, Evanston, IL, in 1994. She did her undergraduate work in electrical and computer engineering at the University of Texas, Austin, from 1999 to 2001, and received the master’s degree from the Department of Electrical Engineering and Computer Science, University of California, Berkeley, in 2003. She is currently working toward the Ph.D. degree at the Electronics Laboratory, Swiss Federal Institute of Technology (l’Ecole Polytechnique Fédérale de Lausanne).

25) Ms. Boucart was the recipient of a National Science Foundation (NSF) Fellowship while in the Department of Electrical Engineering and Computer Science, University of California, Berkeley.

Adrian Mihai Ionescu (S’91–M’93) received the B.S. and M.S. degrees from the Polytechnic Institute of Bucharest, Bucharest, Romania, in 1989, and the Ph.D. degree from the National Polytechnic Institute of Grenoble, France, in 1997.

Grenoble, France, and Stanford University, Stanford, CA, in 1998 and 1999. Since 1999, he has been a Consulting Expert for the Information Society Technologies (IST) program of the European Commission, Brussels, and was recently appointed as National Representative of Switzerland for the European Nanoelectronics Initiative Advisory Council. From 2002 to 2006, he was the Director of the Laboratory of Micro/Nanoelectronic Devices (LEG-2) and served as the Director of the Institute of Microelectronics and Microsystems of the Swiss Federal Institute of Technology (l’Ecole Polytechnique Fédérale de Lausanne), Lausanne, Switzerland, where he is currently an Associate Professor. He has published more than 100 articles in international journals and conferences.

Sakurai, T.: ‘Tunnel perspectives of low-power VLSI’s’, IEICE Trans. Electron., 2004, E87-C, (4), pp. 429–436

Seabaugh, A.C., and Zhang, Q.: ‘Low-voltage tunnel transistors for beyond CMOS logic’, Proc. IEEE, 2010, 98, (12), pp. 2095–2110

Boucart, K., and Ionescu, A.M.: ‘Double-gate tunnel TFET with high-κ gate dielectric’, IEEE Trans. Electron Devices, 2007, 54, (7), pp. 1725–1733 4 Cho, S., Lee, J.S., Kim, K.R., Park, B.G., Harris, J.S., and Kang, I.M.: ‘Analyses on small-signal parameters and radio-frequency modeling of gate-all-around tunneling field-effect transistors’, IEEE Trans. Electron Devices, 2011, 58, (12), pp. 4164–4171

Mookerjea, S., Krishnan, R., Datta, S., and Narayanan, V.: ‘On enhanced Miller capacitance effect in interband tunnel transistors’, IEEE Electron Device Lett., 2009, 30, (10), pp. 1102–1104

Koswatta, S.O., Lundstrom, M.S., and Nikonov, D.E.: ‘Performance comparison between p-i-n tunneling transistors and conventionalMOSFETs’, IEEE Trans. Electron Devices, 2009, 56, (3), pp. 456–465

Koswatta, S.O., Koester, S.J., and Haensch, W.: ‘On the possibility of obtaining MOSFET-like performance and sub-60-mV/dec swing in 1-D broken-gap tunnel transistors’, IEEE Trans. Electron Devices, 2010, 57, (12), pp. 3222–3230

Hraziia, A., Vladimirescu, A., Amara, A., and Anghel, C.: ‘An analysis on the ambipolar current in Si double-gate tunnel FETs’, Solid-State Electron., 2012, 70, pp. 67–72

Abdi, D.B., and Jagadesh Kumar, M.: ‘Controlling ambipolar current in tunneling FETs using overlapping gate-on-drain’, IEEE J. Electron Devices Soc., 2014, 2, (6), pp. 187–190

Verhulst, A.S., Vandenberghe, W.G., Maex, K., and Groeseneken, G.: ‘Tunnel field-effect transistor without gate-drain overlap’, Appl. Phys. Lett., 2007, 91, (5), pp. 053102–053103

Vijayvargiya, V., and Vishvakarma, S.K.: ‘Effect of drain doping profile on double-gate tunnel field-effect transistor and its influence on device RF performance’, IEEE Trans. Nanotechnol., 2014, 13, (5), pp. 974–981

B. Rajamohan, D. Mohata, H. Liu, and S. Datta. Flicker noise characterization and analytical modeling of homo and hetero-junction III-V tunnel FETs. In Device Research Conference (DRC), 2012 70th Annual, June 2012.

V. Saripalli, S. Datta, V. Narayanan, and J. Kulkarni. Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design. In Nanoscale Architectures (NANOARCH), 2011 IEEE/ACM International Symposium on, pages 45–52, 2011.

V. Saripalli et al. An Energy-Efficient Heterogeneous CMP based on Hybrid TFET-CMOS cores. In DAC, 2011.

A. C. Seabaugh and Q. Zhang. Low-voltage tunnel transistors for beyond cmos logic. Proceedings of the IEEE, Dec.

N. Seoane et al. Random dopant, line-edge roughness, and gate workfunction variability in a nano InGaAs FinFET. Electron Devices, IEEE Transactions on, June 2014.

K. Swaminathan et al. Modeling steep slope devices: From circuits to architectures. In Design Automation and Testing in Europe (DATE), 2014.

K. Swaminathan, H. Liu, J. Sampson, and V. Narayanan. An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs (to appear). In International Symposium on Computer Architecture (ISCA), 2014.

P. Theilmann, C. Presti, D. Kelly, and P. Asbeck. Near zero turn-on voltage high-efficiency UHF RFID rectifier in siliconon-sapphire CMOS. In Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE, pages 105–108, May 2010.

A. Trivedi, S. Carlo, and S. Mukhopadhyay. Exploring tunnel-FET for ultralow power analog applications: A case study on operational transconductance amplifier. In Design Automation Conference (DAC), pages 1–6, 2013.



  • There are currently no refbacks.

Copyright (c) 2018 Journal of VLSI Design Tools & Technology

eISSN: 2249–474X