|
Issue |
Title |
|
Vol 8, No 2 (2018) |
A Review on Tunnel Field Effect Transistor for Ambipolar Suppression, Higher ON Current and a Lower Subthreshold Swing |
Abstract
|
Radhika M. Somani, H. R. Upadhyay, K. Sujatha |
|
Vol 4, No 2 (2014) |
A Simple, Compact, and Power-Efficient Current-Mode Decimal Adder Circuit |
Abstract
|
ashish s shende |
|
Vol 4, No 2 (2014) |
A Survey on Recent Approaches for Leakage Power Reduction in MOS Integrated Circuits |
Abstract
|
harshvardhan upadhyay |
|
Vol 8, No 3 (2018) |
A Time Domain Analysis on Chip High Speed VLSI Optical Interconnection Network |
Abstract
|
Abhishek Sharma, Sudhir Kumar Sharma |
|
Vol 6, No 3 (2016) |
A Unified Ultra-Low Power Architecture of Probabilistic Adder Based on GDI Technique |
Abstract
|
B S Patro, srinibasa padhy, monica swain, J K Das |
|
Vol 10, No 2 (2020) |
Adaptive Hysteresis Band Current Controller for the Shunt Active Power Filter Using the d-q0 Reference Frame Theory |
Abstract
|
Subin Chacko, E.M. Suhara, Tiju Baby |
|
Vol 5, No 3 (2015) |
All-Digital Phase Locked Loop (ADPLL) as an Intellectual Property (IP) Core for an Application-specified Integrated Circuit (ASIC) Product: A Survey |
Abstract
|
Rajesh Yadav, Neeraj Kumar Shukla, Rajesh Gupta |
|
Vol 8, No 3 (2018) |
An Area Delay Optimized Carry-Select Adder |
Abstract
|
Sareeka Tulshiram Deore |
|
Vol 1, No 1-2-3 (2011) |
An Explicit Approach to Compare Crosstalk Noise and Delay in VLSI RLC Interconnect Modeled with Skin Effect with Step and Ramp Input |
Abstract
PDF
|
shilpi lavania, sunil kumar sharma |
|
Vol 2, No 1-2-3 (2012) |
An FPGA-based Controller Design for Servo Actuator Using Xilinx System Generator and HDL Cosimulator |
Abstract
PDF
|
T. ananthan, M V Vaidyan, M V Varghese |
|
Vol 2, No 1-2-3 (2012) |
An Innovative Approach of the Analysis of the Low Noise of a CMOS-Based Amplifier for Analog Signal-based Applications |
Abstract
PDF
|
rajinder tiwari, R. K. Singh |
|
Vol 9, No 3 (2019) |
An Outline of Receiver Device Or Gesture Device Components |
Abstract
|
aakanksha shisodia |
|
Vol 10, No 1 (2020) |
An Overview of the Contemporary GSM system in Digital world |
Abstract
|
Soni Bisht |
|
Vol 9, No 3 (2019) |
An Overview to Transmitter Device Or Gesture Device Components |
Abstract
|
shraddha singh |
|
Vol 6, No 2 (2016) |
Analysis and Characterization of Different Topologies of Dynamic Latch based CMOS Comparators for Delay, Offset and Power |
Abstract
|
Vijay Savani, N M Devashrayee |
|
Vol 7, No 1 (2017) |
Analysis and Implementation of Folding and Interpolating Analog to Digital Converter using Submicron CMOS Technology |
Abstract
|
rahulkumar S suthar, priyesh P gandhi |
|
Vol 1, No 1-2-3 (2011) |
Analysis of Resource Utilization for a Floating-Point Complex Multiplication in FPGA |
Abstract
PDF
|
anitha Mary |
|
Vol 12, No 1 (2022) |
Analysis of Six-Pulse Bridge Circuits Including Zener and Semiconductor Diodes Part One |
Abstract
|
Mohamed M. Saied |
|
Vol 12, No 2 (2022) |
Analysis of Six-Pulse Bridge Circuits Including Zener and Semiconductor Diodes – Part Two |
Abstract
|
Mohamed Mostafa Saied |
|
Vol 11, No 3 (2021) |
Analysis of Three Phase AC-DC Front End Converter with Vector Control |
Abstract
|
Kunjan Bhanderi |
|
Vol 1, No 1-2-3 (2011) |
Analysis of VLSI Circuits Designed with Single and Dual Channel Strained Silicon MOSFETs in Nanoregime |
Abstract
PDF
|
neha sharan, ashwani rana |
|
Vol 11, No 2 (2021) |
Appliance Scheduling Optimization for Demand Response: A Review |
Abstract
|
Shubham ., Sandeep . |
|
Vol 8, No 2 (2018) |
Area and Power Improvement with New Initial Ordering Method Combined with Sift Algorithm for BDD Mapped Circuits |
Abstract
|
M. Balal Siddiqui, M. T. Beg, S. Naseem Ahmad |
|
Vol 6, No 3 (2016) |
Area Efficient Layout Design of Two Bit Magnitude Comparator Using Novel Strategy |
Abstract
|
shashank gautam, pramod sharma |
|
Vol 10, No 1 (2020) |
Artificial Intelligence Techniques in Switchgear and Protection |
Abstract
|
Harshal D. Vaidya, Pandurang G. Kate, Balaji R. Jadhav |
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