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Dynamic Comparators for Very High-Speed ADC’s

Dr. J. Geetha Ramani, Swapna S., Priyadharshini .S


The need for ultra- low power and space economical analog –to- digital converters (ADCs) is pushing towards the utilization of low voltage CMOS dynamic comparators to maximise the facility potency and speed. the traditional dynamic comparators have options like high input ohmic resistance, no static power dissipation and sensible strength against noise and couple. the downside is that giant numbers of transistors are accustomed minimize the offset, therefore the speed of the comparator is degraded. Double tail comparators overcome the drawbacks in typical comparator by reducing the stacking of transistors with low provide voltage with less delay. However the trans-conductance is low for this comparator. In low power double tail comparator, whilenot complicating the look and by adding few transistors feedback within the regeneration is strong with ends up in reduced delay time. During this paper delay analysis of various dynamic comparators are given  with  relevance  speed and provide voltage. Then supported the delay analysis results, the traditional dynamic comparator is changed in terms of electronic transistor technology and design results as body driven comparator for quick operation even in immoderate low provide voltages. Simulation ends up in 90nm CMOS technology reveals that the delay time is reduced.


Terms—Dynamic Comparators, Double Tailcomparators, Body driven comparator, Regeneration, Delay Analysis

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J. He, S. Zhan, D. Chen and R.J. Geiger,” Analysis of static and dynamic random offset voltages in dynamic comparators,” IEEE Trans. Circuits and Syst. I, reg. papers, vol.56, no.5, pp.911-919, May-2009.

B. Goll and H. Zimmermann,” A comparator with reduced delay time in 65nm CMOS for power supply voltages down to 0.65,” IEEE Trans. Circuits and Syst, II Exp. Briefs, vol.56, no.11,pp 810-814, Nov-2009.

S. Babayan-Mashhadi and R. Lofti,” An offset voltage cancellation technique for comparators using body-voltage trimming,” Int. J. Analog Circuits Signal Process., vol.73, no.3, pp.673-682, Dec-2012

A. Mesgarani, M. N. Alam, F. Z. Nelson, and S. U. Ay, “Supply boosting technique for designing very low-voltage mixed-signal circuits in standard CMOS,” in Proc. IEEE Int. Midwest Symp. Circuits Syst. Dig. Tech. Papers, Aug. 2010, pp. 893–896.

B. J. Blalock, “Body-driving as a Low-Voltage Analog Design Technique for CMOS technology,” invited paper in the IEEE proceedings of the Midwest Symp. On Mixed-signal design, pp. 113-118, 2000.

S. Babayan-Mashhadi and R. Lofti,” Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator,” IEEE Trans. VLSI Syst, vol.22, no.2, pp.343-352, Feb-2014

R. Jacob Baker, CMOS Circuit Design, Layout and Simulation, Wiley Publications, Third Edition.

P.M. Figueiredo and J.C. Vital” Kickback noise reduction for CMOS latched comparators,” IEEE Trans, Circuits Syst. II, Exp. Briefs, vol.53, no.7, pp 541-545, July-2006

S. Babayan-Mashhadi and M. Sarvaghad-Moghaddam,” Analysis and Design of Dynamic Comparators in ultra-low supply voltages,” in 22nd Iranian Conference on Electrical Engineering (ICEE), May 2014.


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