Effect of Various Parameters on Threshold Voltage of Virtually Fabricated Lightly Doped PMOS Device

Nitin Sachdeva, Munish Vashishath, P. K. Bansal

Abstract


This paper emphasis on the design, fabrication and analysis of 45 nm P type MOSFET device using SILVACO TCAD tool. The analysis was based on variation of various parameters like oxide thickness, threshold implant and halo implant (pockets) to analyze the threshold voltage. The drain versus gate and drain versus gate plots are being plotted using tony-plot. It has been observed that as the thickness of the oxide increases, threshold voltage also increases. Various other parameters like on current, off current, On/Off current ratio and DIBL has also been calculated for different oxide thicknesses. From the simulation results, the optimum threshold voltage of -0.026 V has been achieved.

Keywords: MOSFET, SILVACO, threshold voltage, DIBL, Athena

Cite this Article

Nitin Sachdeva, Munish Vashishath, P. K. Bansal. Effect of Various Parameters on Threshold Voltage of Virtually Fabricated Lightly Doped PMOS Device. Journal of VLSI Design Tools & Technology. 2017; 7(3): 13–20p.


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References


J. M. Rabey and M. Pedram, “Low Power Design Methodologies,” Kluwer Academic Publishers, Fifth Print 2002, ch. 2, pp. 39.

BSIM 4.6.4 MOSFET Model -User's Manual, T. Hasan M. Wenwei (Morgan) Yang, V. Mohan Dunga, 2009, pp. 39

The International Technology Roadmap for Semiconductors www.itrs.net

K. A. Gupta, V. Venkateswarlu, D. Anvekar, and S. Basu, "The Impact of Channel-Width on Threshold Voltage for Short Channel Devices," in Proc. IEEE Region 10 conference TENCON 2011- Circuits and Systems, Indonesia, November 2011, pp. 715-719.

Ch, A. , Ravindra, J. and Lalkishore, K. (2015) Design of Ultra-Low Power PMOS and NMOS for Nano Scale VLSI Circuits. Circuits and Systems, vol 6, pp-60-69.

Kiran A Gupta, Dinesh K Anvekar and V.Venkateswarlu “A Comparative Study and Analysis of Short Channel Effects for 180nm and new 45nm transistors” Published by Springer Journal book series in Advances in Intelligent and Soft Computing, Vol.178 Series. July 2012. Pg.377-387

Ninomiya, S. et al. (2009). Vth Control by Halo Implantation using the SEN's MIND System, The 9th International Workshop on Junction Technology, pp. 100-103.

Fauziyah Salehuddin, Ibrahim Ahmad, Fazrena Azlee Hamid, Azami Zaharim, (2009). Application of Taguchi Method in Optimization of Gate Oxide and Silicide Thickness for 45nm nMOS Device, International Journal of Engineering & Technology (IJET), Vol. 9 No. 10. pp. 94-98.




DOI: https://doi.org/10.37591/jovdtt.v7i3.1

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