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A 32-Bit Booth Multiplier Design Using GDI Logic Style

Bharat H. Nagpara

Abstract


Gate diffusion input (GDI) is the newest technology of designing a low-power digital combinational circuit. This logic allows reducing power dissipation, delay and area of any digital logic circuit. The gate diffusion input logic allows implementation of a wide range of any complex logic function. These functions can be realized using only two transistors. This technique is preferred for designing fast using less number of transistors while improving logic level for swing and static power characteristics and also allows simple design by using smaller cell library. Comparison of GDI transistor count with CMOS is also compared power dissipation and delay. Simulation result shows that the proposed GDI logic has been good in performance in comparison to CMOS logic design. In this paper, the 32-bit booth multiplier is designed based on GDI logic and the simulations are performed by using Tanner tool based on 45 nm CMOS process technology. Good results have been achieved in terms of power dissipation and delay.

 

Keywords: Booth multiplier, GDI logic, CMOS technique, 45 nm technology, Tanner EDA simulation result


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