A Reliable Routing Architecture and Algorithm for Network-on-Chip

Abstract

The Network-on-Chip (NoC) is Network-version of System-on-Chip (SoC) means that on-chip communication through packet based networks. In NOC topology, routing algorithm and switching are main terminology. The routing algorithm is one of the key factors in NoC architecture. The routing algorithm which defines as the path taken by a packet between the source and the destination. The paper proposes a novel algorithm for a Network-on-Chip, which is based on packet switching. Using square mesh techniques used for 16 nodes based NoC design and simulation. The node is equal to row and column. Paper discusses internal architecture of NoC using addressable memory and simulate on XILINX 14.1 ISE MODELSIM.