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Design and Implementation of Low Power Priority Encoder

C. Ramesh Kumar Reddy, Koneti Anusha, K. Aravind Kumar, G. Eshwar Raj


Nowadays, low-power devices are widely used in VLSI design technology because they can reduce power consumption and power dissipation. To achieve this, various low-power techniques are utilized to minimize device power losses. This project focuses on analyzing the performance of priority encoders in different low-power technologies for Flash Type ADC. Moreover, the power consumption of these technologies is compared with the conventional CMOS design. Each of these techniques offers distinct benefits depending on the operational logic. The purpose of this project is to compare low-power techniques to arrive at the optimal technique for designing a low-power priority encoder for a flash ADC A low-power priority encoder implementation in a flash ADC arrives at the best design among the low-power techniques referenced and compared from the literature.


Priority Encoder, CMOS, PTL, LECTOR Technique, GDI, Transmission gate

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