Artificial Neural Network Implementation in FPGA using Multiplexer-based Weight Updating for Efficient Resource Utilization

Abstract

This paper presents a novel scheme for field-programmable gate array (FPGA) implementation of an artificial neural network (ANN). The proposed implementation is aimed at reducing resource requirement, without compromising on the speed so that a complex ANN architecture could be realized on a single chip at a lower cost. The weight updating process in different layers of the ANN has been carried using a simple MUX-based architecture. Backpropagation algorithm which typically requires a large number of multipliers for weight updating has been used to train the network. The proposed technique has proven to be very effective in reducing resource requirements at the cost of a moderate overhead on speed. This implementation is expected to make hardware implementation of back propagation algorithm trained ANNs viable in terms of cost and speed for real time applications.