Open Access Open Access  Restricted Access Subscription or Fee Access

Flip chip package to revive authenticated proclaim

Bangshidhar Goswami

Abstract


This article is described to access optimal manufacture process for flip-chip package. Method of electrical connection has subjected in flip chip to describe interlink of die to package carrier. Connection from die to exterior of package has thus, dealt by package carrier that has been either substrate or lead-frame. Interconnection between die and carrier has made using wire to subject standard package. Nevertheless, advanced technology nodal device fabrication has scriptive issued use Cu/low-K stack after improve of following criteria. Low-K dielectric has subtended sensitivity from assemble and pack stresses, subjective has linked to incur inferior mechanical properties than convened dielectric materials. Suggestive issued has investigated clue by finite element analysis (FEM) method to assure package reliability.

Keywords


Flip chip, Ball grid array, Solder, Cu-pillar, Packaging, Photoresist

Full Text:

PDF

References


Wire bonding. (n.d.) McGraw-Hill Dictionary of Scientific & Technical Terms, 6E. (2003). Retrieved November 15 2021 from https://encyclopedia2.thefreedictionary.com/wire+bonding; wire bonding; https://encyclopedia2.thefreedictionary.com/wire+bonding

Silicon Valley Campus (HQ); Sierra Circuits, Inc., 1108 West Evelyn Avenue, Sunnyvale, CA 94086, Toll free: (800) 763-7503. Fax: (408) 735-1408

X.R. Zhang, W.H. Zhu, B.P. Liew, M. Gaurav:, A. Yeo and K.C. Chan: Copper Pillar Bump Structure Optimization for Flip Chip Packaging with Cu/Low-K Stack; 11th. Int. Conf. on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSimE 2010Conference Paper · May 2010; DOI: 10.1109/ESIME.2010.5464565 · Source: IEEE Xplore; https://www.researchgate.net/publication/224138191

Dennis Crapse, Warren W. Flack, Ha-Ai Nguyen, Elliott Capsuto, Craig McEwen: Performance of a 55 Micron Copper Pillar Bump Process Using a Positive Thick Chemically Amplified Photoresist; SPIE 2007 #6519-174

Mohammed Genanu, Babak Arfaei, Eric J.Cotts, Francis Mutuku, Eric Perfecto, Scott Pollard, Aric Shorey: MICROSTRUCTURE AND PERFORMANCE OF MICRO CU PILLARS ASSEMBLIES; Proceedings of SMTA International, Sep. 25 - 29, 2016, Rosemont, IL, USA Page 75

Tsai, M.-Y.; Wang, Y.-W.; Liu, C.-M. Thermally-Induced Deformations and Warpages of Flip-Chip and 2.5D IC Packages Measured by Strain Gauges. Materials 2021, 14, 3723. https://doi.org/ 10.3390/ma14133723

Y. K. SHEN, S. H. CHEN AND H. C. LEE: Analysis of the Mold Filling Process on Flip Chip Package; Journal of REINFORCED PLASTICS AND COMPOSITES, Vol. 23, No. 4/2004; 407

Seungbae Park, H. C. Lee, Bahgat Sammakia, and Karthik Raghunathan: Predictive Model for Optimized Design Parameters in Flip-Chip Packages and Assemblies; IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 30, NO. 2, JUNE 2007; 294

Chiang-Ho Cheng, An-Shik Yang, Chih-Jer Lin, and Chun-Ta Chen: Settling Studies of Underfill Particles for Flip-Chip Solder Interconnections; Proceedings of the World Congress on Engineering 2013 Vol III, WCE 2013, July 3 - 5, 2013, London, U.K

Y. H. Guu, Kuen-Yi Lin, Lung-Sheng Lee: IDENTIFYING PROFESSIONAL COMPETENCIES OF THE FLIP-CHIP PACKAGING ENGINEER IN TAIWAN; TOJET: The Turkish Online Journal of Educational Technology – October 2014, volume 13 issue 4; 61


Refbacks

  • There are currently no refbacks.


Copyright (c) 2021 Journal of Semiconductor Devices and Circuits

Publisher: STM Journals, an imprint of CELNET (Consortium e-Learning Network Pvt. Ltd.)

Address: A-118, 1st Floor, Sector-63, Noida, Uttar Pradesh-201301, India

Phone no.: 0120-478-1215/ Email: [email protected]