Design and Simulation of Ternary Gates Using Fin-FET

Abstract

In recent years, digital communication system has becomes more popular. But the on-chip interconnections have become a major problem as more and more modules are packed into a chip by reducing the gate size. As the gate size is reduced further the complexities in the circuit increases. Binary logic circuit dissipates a lot of energy, increase processing time, and causes coupling effect. In the Ternary logic system, there are three states having a value of 0, 1 and 2. This increase in number of states helps in increasing the number of bit-hand ling capability with less circuit elements. The previous literature shows that the Fin-FET device is not explored for the design of ternary logic. This paper presents the design and implementation of ternary logic circuits using the circuit model of Fin-Field Effect Transistor (Fin-FET). The design of various Fin-FET gates, including T-NAND, T-NOR, T-AND, T-OR, T-EX-OR and T-EX-NOR are demonstrated. The physical design of the circuits is simulated and tested with T-SPICE simulator. The performance characteristics like rise/fall time, noise margin and power delay product for different loads and frequencies are calculated and analyzed. The proposed Ternary logic gate design provides an improved transient performance and Power delay product compared to the conventional binary logic gate design technique