3D Simulation of Multi-Gate Mosfet Analysis for Analog Circuit Design Parameters

Authors

  • Nirmal D Department of Electronics and Communication Engineering, Karunya University, Coimbatore 641114, Tamilnadu, India
  • Thaya J. S. Department of Electronics and Communication Engineering, Karunya University, Coimbatore 641114, Tamilnadu, India
  • Manoj S. Department of Electronics and Communication Engineering, Karunya University, Coimbatore 641114, Tamilnadu, India
  • Lyndon B. G. Department of Electronics and Communication Engineering, Karunya University, Coimbatore 641114, Tamilnadu, India
  • Jebalin B. K. Department of Electronics and Communication Engineering, Karunya University, Coimbatore 641114, Tamilnadu, India
  • Chacko J. K. Department of Electronics and Communication Engineering, Karunya University, Coimbatore 641114, Tamilnadu, India

DOI:

https://doi.org/10.37591/josdc.v1i2.5171

Abstract

Chip density and performance improvements of semiconductor devices have been driven by their aggressive scaling. The performance of multi-gate FET for analog applications is explored in this paper.  Analog operation of CMOS devices and its parameters are very important for future cutting edge technologies. The multi-gate technology shows excellent scalability and better immunity to short channel effects in MOSFETs. They are being easily assessed for CMOS applications beyond the 45 nm of the SIA roadmap 2010. Moreover, the optimization of the tri-gate device is done by varying the length of the three gates. The scalability of nanoscale device is done and the comparison of the threshold voltage, Ion current, Ioff current, Ion/Ioff ratio, and transconductance for different multi-gate FET structures are analyzed.

 

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Published

2021-01-25

Issue

Vol. 1 No. 2 (2014)

Section

Research Articles