Design, Verification and Circuit Level Implementation of a Ballistic MOSFET

Authors

  • Arun Kumar Chatterjee Department of Electronics and Communication Engineering, Thapar Institute of Engineering and Technology (formerly known as Thapar University), Patiala, Punjab, India
  • B. Prasad Department of Electronic Science, Kurukshetra University, Kurukshetra, Haryana, India

DOI:

https://doi.org/10.37591/jovdtt.v8i3.1201

Abstract

A drain current expression is obtained for a nanoscale ballistic MOSFET within the framework of Landauer-Buttiker formalism considering intrinsic silicon channel at low temperature. The model drain current is compared with the numerical simulations of near ballistic nanoMOSFET structure. There is a reasonable agreement between the model and the numerical simulation results. This demonstrates the remarkably low value of the subthreshold slope of ballistic nanoMOSFET. Further, the design structure is incorporated in an inverter circuit which works well verifying its functionality in the integrated circuits.


Keywords: Ballistic MOSFET, charge density, triangular potential well, wave function, drain current

Cite this Article
Arun Kumar Chatterjee, Prasad B. Design, Verification and Circuit Level Implementation of a Ballistic MOSFET. Journal of VLSI Design Tools & Technology. 2018; 8(3): 15–22p.


Author Biography

  • Arun Kumar Chatterjee, Department of Electronics and Communication Engineering, Thapar Institute of Engineering and Technology (formerly known as Thapar University), Patiala, Punjab, India
    A.P., ECED,

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Published

2018-12-03

Issue

Vol. 8 No. 3 (2018)

Section

Articles

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