Implementation of DCC technique using differential amplifier based filter in 90nm CMOS technology

Authors

  • Lalita Machhindra Landge
  • Usha Jadhav

DOI:

https://doi.org/10.37591/jovdtt.v9i2.1329

Abstract

Analog technique with feedback loop is applied to correct the duty cycle of any circuit without using more power. Pulse width modification is used to vary the duty cycle of clock signal. PMC cell is designed for expansion and contraction of pulse width. Differential amplifier based filter is used to detect the duty cycle of the particular clock signal. Differential amplifier and OpAmp are used to achieve adequate gain. The simulation is done in tanner EDA version_13 tool by using standard 90 nm technology. The schematic layout design of proposed DCC architecture is created in S-Edit. The system works at the frequency range of about 1 to 5 MHz.


Keywords: Pulse width modification, duty cycle, delay locked loop, noise, sensitivity

Cite this Article

Lalita Landge, Usha Jadhav. Implementation of DCC Technique Using Differential Amplifier Based Filter in 90nm CMOS Technology. Journal of VLSI Design Tools & Technology. 2019; 9(2): 16–25p.

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Published

2019-07-16

Issue

Vol. 9 No. 2 (2019)

Section

Articles

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