Implementation and Analysis of 32-bit pipelined RISC Processor Architecture

Authors

  • P. Indira Research Scholar, Department of Electronics and Communication Engineering, Chimanlal Ujamshibhai Shah University, Wadhwan, Gujarat, India
  • M. Kamaraju Professor, Department of Electronics and Communication Engineering, Jawaharlal Nehru Technological University, Kakinada, Andhra Pradesh, India

DOI:

https://doi.org/10.37591/jovdtt.v9i1.1528

Abstract

Pipelining is an implementation technique, in which parallel operations are performed for several instructions simultaneously, to save time, enhance speed and for better utilization of hardware units. In this paper, 32-bit, 5-stage RISC processor is used to tag the pipeline stages to obtain the optimized results. The architecture of the processor containing several elements reduces the debugs and upholds the high performance through critical functions. When compared to our closest counterpart in implementing the pipeline technique, the occupied area of our model is reduced by 25%; and leads speed by 52%. The simulation and synthesis is carried out by the Xilinx platform with supported MATLAB graphs to describe the relationship between various parameters.


Keywords: RISC processor, Xilinx, MATLAB, pipelining

Cite this Article

P. Indira, M. Kamaraju. Implementation and Analysis of 32-bit Pipelined RISC Processor Architecture. Journal of VLSI Design Tools & Technology. 2019; 9(1): 1–14p.

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Published

2019-03-01

Issue

Vol. 9 No. 1 (2019)

Section

Articles

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