Design and Analysis of an Efficient Fast Low Power 1 Kb SRAM Cell Using 90nm and 45 nm Microwind Technology

Authors

  • A.K. Pathrikar Department of Electronics and Communication, DIEMS, Aurangabad, Maharashtra, India
  • Rajkumar S. Deshpande CSMCoE, Nepti, Ahmednagar, Maharashtra, India

DOI:

https://doi.org/10.37591/jovdtt.v5i2.1588

Abstract

This paper proposes a review on study and analysis of an efficient fast low power 1 Kb SRAM cell using 90 and 45 nm Microwind technology. In this paper we have proposed the tentative improvement in performance parameters of SRAM cell like power dissipation, read or write speed, stability and signal to noise margin ration (SNM) using CMOS scaling.

Keywords: SRAM, CMOS scaling, Microwind

Cite this Article

Pathrikar A.K, Deshpande Rajkumar S. Design and Analysis of an Efficient Fast Low Power 1 Kb SRAM Cell Using 90 and 45 nm Microwind Technology. Journal of VLSI Design Tools and Technology (JoVDTT). 2015; 5(2): 1–3p.


Downloads

Published

2019-02-13

Issue

Vol. 5 No. 2 (2015)

Section

Articles

License

Thank you for submitting the manuscript to the Journal of VLSI Design Tools & Technology. With the online journal management system that we are using, you will be able to track its progress through the editorial process by logging in to the journal web site:

An author may request for withdrawal of his/her manuscript, within a week's
time  (w.e.f. the date of submission of the manuscript). The Author is
recommended to follow strictly the Instructions in Manuscript Withdrawal
Policy (As per URL given below)
http://stmjournals.com/pdf/manuscript%20withdrawl.pdf


If you have any questions, please contact me. Thank you for considering this
journal as a venue for your work.