Review of Design and Implementation of Adder with Increasing Bits by Using Constant Delay Logic Style
DOI:
https://doi.org/10.37591/jovdtt.v5i2.1599Abstract
A different logic style including the constant logic style is proposed in this paper which is helpful in increasing the high speed applications. It is suitable for implementing the complicated arithmetic expressions. The objective of this paper is to reduce the delay, noised margin and power consumption. The transistor for minimal power delay product and energy delay product is proposed in this paper. The design and implementation of adder in different bits as 8, 16, 32 and 64 bits; by comparing their results with and without constant delay logic styles. With the proposed simulation, it is shown that the reduced power delay product and energy delay product, and increased the efficiency of higher adder performance.
Keywords: Adder, carry look ahead, high performance, high speed, low power, constant delay, feed through
Cite this Article
Megha Hulkey, Harshvardhan Upadhyay. Review of Design and Implementation of Adder with Increasing Bits by using Constant Delay Logic Style. Journal of VLSI Design Tools and Technology (JoVDTT). 2015; 5(2): 38–41p.
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