All-Digital Phase Locked Loop (ADPLL) as an Intellectual Property (IP) Core for an Application-specified Integrated Circuit (ASIC) Product: A Survey

Authors

  • Rajesh Yadav Department of Electrical and Electronics Engineering, ITM University, Gurgaon, Delhi-NCR, India
  • Neeraj Kumar Shukla Department of Electrical and Electronics Engineering, ITM University, Gurgaon, Delhi-NCR, India
  • Rajesh Gupta Cadence Design System, Noida, Delhi-NCR, India

DOI:

https://doi.org/10.37591/jovdtt.v5i3.1646

Abstract

An all-digital phase locked loop (ADPLL) plays a great role in decreasing the development time of an application-specified integrated circuit (ASIC) products and helps to meet the time-to market requirement of product, because an ADPLL can be used as an IP core, so it is easily reusable in any design. Now a days ADPLL is being widely used in various fields such as control systems and digital communication systems. This survey paper presents the basic details of ADPLL and its recent developments in ADPLL. Implementation and function of each component of ADPLL has been described separately.

Keywords: ADPLL, DCO, frequency phase detector, loop filter, HDL, SoC, IP core

Cite this Article

Rajesh Yadav, Neeraj Kumar Shukla, Rajesh Gupta. All-Digital Phase Locked Loop (ADPLL) as an Intellectual Property (IP) Core for an Application-Specified Integrated Circuit (ASIC) Product: A Survey. Journal of VLSI Design Tools and Technology. 2015; 5(3):  12–17p.


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Published

2019-03-11

Issue

Vol. 5 No. 3 (2015)

Section

Articles

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