A New High Speed Low Power 1 Bit Full Adder
DOI:
https://doi.org/10.37591/jovdtt.v3i1.2807Abstract
This paper proposes a low power, low area and high speed 1-bit full adder compared to earlier 1bit full adder designs. The adder comprises of eight transistors with some modifications over the other existing design, so that it can invariably be used in the device with least nano device dimensions. The proposed design exhibits lower threshold loss and works faithfully in sub-threshold regime with appreciable voltage swing at lower power supply of 0.5 V. The simulation has been carried out using Cadence Virtuoso Spectre at 45 nm technology.
Keywords: design and simulation, full adder, low power, nanoscale, sub-threshold
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