Reconfiguring CMOS Driver and Receiver Pair as Pseudo NMOS for Low-swing Signaling On-chip Interconnects

Abstract

The Low power bus architecture [9, 12, 13] consists of Driver, Receiver and Interconnects in between them inside the Chip. The Low power bus architecture [1] models are classified in to Symmetric and Asymmetric [7, 11, 14, 15] based on low voltage scaling technique and very simple design principles were utilized to construct driver, receiver and interconnects. The low power bus driver has the ability to switch from a low swing to high swing mode. The receiver can be a simple inverter. The bus architecture consists of a driver which has an input the nominal voltage value level and decreases the voltage swing on the bus line (or the output load); and a receiver which regenerates the proper voltage levels in order to ensure the compatibility with the attached circuits. These bus architectures are designed in conventional CMOS technology and Pseudo NMOS technology. These bus architectures were implemented on 2.0 V 0.25μm CMOS technology using T-Spice (Monte Carlo Simulation), for signal transmission along a wire-length of 3, 6, and 10 mm and the extra fan-out load of 0.12 pF (on the wire). The performance of each of the presented circuits is thoroughly examined using simulation on a test benchmark interconnect circuit (i) RC─π (N) type (where N = 1, 2, 3), (ii) RC−L type. Comparisons of the proposed architecture with conventional CMOS architecture are presented as well, indicating a significant saving in power due to low voltage scaling. The advantages of the proposed architectures are that they require only one power supply and threshold voltage as well as less area, hence significantly reducing the design complexity.

Key words: pseudo NMOS logic design, previous and present digital CMOS design, 0.25μm technology, bus architecture, and interconnect length, low power and performance tradeoffs