High Speed Low Offset Power Efficient Fully Differential Double Tail Dynamic Comparator

Abstract

This paper comprises a novel fully differential double tail high performance comparators suitable for low-voltage low-power applications.  A fully differential double tail comparator has been designed to meet the requirement of high speed, low power consumption with low offset voltage. Authors have proposed novel architecture of dynamic voltage comparator which is differential and double tail and verified the architecture by simulation in TSMC 180nm technology with ±0.9V supply. The proposed comparator has very wide dynamic range, low offset, low propagation delay with less power dissipation. The power consumption of the proposed comparator 43% less as compared to conventional comparators with improved dynamic range and very low offset voltage.

Keywords- CMOS, Comparator, FDDC, FDDTDC, Offset, ICMR, Power Dissipation.