Comparative Analysis of Low-Power Adiabatic Techniques

Abstract

In today’s modern era, new revolutionary designs are replacing old traditional bulky designs. Due to advancements in technology, low-power designs are in demand. Advantages of adiabatic technique can be used for overcoming disadvantages of typical CMOS such as dissipated energy loss. Adiabatic techniques are extremely reliant on parameter changes. In this paper, the merits of adiabatic techniques are depicted on the basis of parameter variations. By the use of SPICE simulation, traditional CMOS inverter is compared with two adiabatic techniques, positive feedback adiabatic logic (PFAL) inverter and efficient charge recovery logic (ECRL) inverter on 125 and 90 nm technology. The results show that adiabatic logic circuits are better energy-reducing techniques than typical CMOS logic circuit.

Keywords: Clock power, adiabatic switching, energy dissipation, AC power supply, ECRL logic circuit, PFAL logic circuit