Decimator Design for Sigma-Delta ADC

Authors

  • Narendra Bahadur Singh Central Electronics Engineering Research Institute(CSIR-CEERI), Pilani, Rajasthan-333031
  • tripti sharma
  • prashant singh

DOI:

https://doi.org/10.37591/jovdtt.v2i1-2-3.2945

Abstract

This paper describes the design of a decimator which is used in digital signal processing as well as 10-bit sigma-delta analog-to-digital converter to down sample the incoming signal for further applications. It is also used for verification of the sigma-delta modulator functionality to reconstruct the incoming signal. The design has been carried out using 180 nm TSMC, CMOS foundry parameters for spice level 49 model parameters in TANNER EDA (Tspice). The results for the presented decimator model are mentioned in the paper; the higher decimation factor can be taken similarly as per requirement.

 

Keywords: DSP, decimator, counter, sigma-delta ADC, DAC, operational amplifier

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Published

2019-08-08

Issue

Vol. 2 No. 1-2-3 (2012)

Section

Articles

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