Performance Estimation of VLSI Design

Authors

  • Pritam Bhattacharjee

DOI:

https://doi.org/10.37591/jovdtt.v4i2.3167

Keywords:

Propagation delay, NMOS, PMOS, Rise Time, Fall Time, Elmore Delay, Layout

Abstract

This paper explores performance estimation of VLSI design using simple RC delay model based an Elmore Delay Method. In this paper Pre-layout & Post-layout VLSI design flow for delay convergence is also shown.

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Published

2019-08-16

Issue

Vol. 4 No. 2 (2014)

Section

Articles

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