Low Power Area Efficient 4×4 Vedic Multiplier using GDI half adders with Better Delay Performance

Abstract

In the field of VLSI, wireless communication and digital signal processing, low power and area efficient architectures are considered. Majority of such applications uses multiplication. The multiplication is done using repetitive addition and shift and add method. It consumes more area delay and power. Vedic multiplier is one of the efficient multiplier. It is designed using different Vedic techniques or sutras, which reduces the area, power consumption and provide better delay performance. In this paper a Vedic multiplier is designed using GDI half adders and full adders. The full adders are made with these GDI half adders. The GDI half adders are low power and area efficient than PTL and conventional half adders. The proposed Vedic multiplier is area efficient, consumes less power and better delay when compared to Vedic multiplier using pass transistor logic (PTL).Simulations are done using cadence virtuoso in 180 nm technology. Power, delay and no of transistors are the performance parameter.
Keywords: Vedic multiplier, pass transistor logic (PTL), GDI technique (Gate Diffusion Input), CADENCE VIRTUOSO (Tool)