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Analysis and Design of Decoder Using Different Adiabatic Technique

Pankaj ., Bal Krishan

Abstract


Abstract

The CMOS logic circuit depends upon charging and discharging of the capacitive load. This is one of the major sources of power dissipation. Adiabatic circuits are used to minimize the power dissipation. These circuits are based on feeding the charge back to power supply instead of discharging it to ground. The paper presented here is based on adiabatic logic style, PFAL (Positive Feedback Adiabatic Logic) and DFAL (Diode Free Adiabatic Logic). 2:4 DECODER using these techniques are studied and power results are compared with conventional CMOS logics. In this technique average power is minimized and the simulation has been done in Tanner EDA Tool using 180 nm technology. Power Dissipation in DFAL is minimized by 25.601% and by 16.459% in PFAL as compared to conventional CMOS. So we can conclude that DFAL is better than PFAL and conventional CMOS.

 Keywords: Tanner, CMOS, adiabatic logic, PFAL, DFAL

Cite this Article

Pankaj, Bal Krishan. Analysis and Design of Decoder Using Different Adiabatic Technique. Journal of Electronic Design Technology. 2018; 9(1): 24–29p.



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