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Impact of Xilinx ISE Design Suite’s MAP and Generate Programming Optimization Settings on FPGAs Bitstream Size

Pravin N. Matte, Dilip D. Shah

Abstract


Abstract

In SRAM based FPGA configuration bitstream resides in configuration memory. Bitstream contains information of CLBs, IOBs and logic interconnects. With increase in complexity of design, size of bitstream increases. Hence if size of bitstream is reduced, less configuration memory required. CAD tools used in FPGA based design has different settings which affects logic capacity, performance speed, resource utilization, power consumption, area required for placing designs etc. In this paper, we have investigated impact of Xilinx ISE design suite’s MAP optimization settings and compression option found in generate programming file on bitstream size. We observed that bitstream size reduces with software settings of CAD tool as compared with its default settings. Overall 47.91% compression ratio is obtained for benchmark designs and optimized settings of Xilinx ISE Design Suite 14.7.

 Keywords: Bitstream, CAD, Configuration, FPGA, ISE, Optimization, Xilinx

Cite this Article

Pravin N. Matte, Dilip D. Shah. Impact of Xilinx ISE Design Suite’s MAP and Generate Programming Optimization Settings on FPGAs Bitstream Size. Journal of Electronic Design Technology. 2018; 9(1): 1–8p.


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