THD Minimization of 27 Level Inverter using FPGA Control Strategy

Abstract

Normally single phase inverter gives only +230 V or –230 V. But multilevel inverter gives the variable output voltage in various levels and also the harmonics are reduced.
If harmonics are produced, it affects the output of the load. Most of the industrial applications rely on Induction motors because of the reliable operation, low cost and simple construction. So the Multilevel inverter output is connected to the Induction motor. Here FPGA digital controller is used to reduce the switching loss. The VHSIC Hardware Description Language (VHDL) coding reduces the program complexity. In this project, a new Hybrid Multilevel Inverter is designed for Induction motor drives where it focuses on Asymmetrical topologies. The proposed method introduces 27 levels Inverter fed Induction Motor drive using 12 switches. With the use of high level inverter, resolution is increased and also the THD is highly reduced.

Keywords: total harmonic distortion (THD), induction motor (IM), field programmable gate array (FPGA)