Open Access Open Access  Restricted Access Subscription or Fee Access

A Novel Logic Styles used for Leakage Power Reduction in MOS Integrated Circuit

M. Hulkey, H. Upadhyay, K. Sujhatha

Abstract


Modified constant delay logic style and clocked logic style is defined by comparing their result. In this paper, a design technique has been proposed which reduces the power dissipation. The design and implementation of full adder and ripple carry adder with constant delay logic. The leakage power has become a serious concern in CMOS technologies that has been solved by the MCD and clocked logic style. Constant delay logic style is having two blocks and having a unique characteristic at which we get pre-evaluated output. But the new proposed modified constant logic style and clocked logic style provides better result than the constant logic style. The CMOS technology is used for the simulation process by which the parameter of power is measured which is compared with constant delay logic style.

 

Keywords: CMOS, power consumption, full adder, ripple carry adder, high performance, inverter, adder, constant delay


Full Text:

PDF

Refbacks

  • There are currently no refbacks.


Copyright (c) 2019 Journal of VLSI Design Tools & Technology



eISSN: 2249–474X