Vol. 6 No. 1 (2016)

Articles

• A Novel Logic Styles used for Leakage Power Reduction in MOS Integrated Circuit

  M. Hulkey, H. Upadhyay, K. Sujhatha

  1-5

  • Requires Subscription PDF (USD 30)

• Hardware Implementation of Configurable Multi Image Fusion

  S S. Malwadkar, W M. Mendre, S S. Agrawal

  6-15

  • Requires Subscription PDF (USD 30)

• A Review for Power Optimization in MOS Devices using Different Logic Styles

  M. Hulkey, H. Upadhyay, K. Sujatha

  16-20

  • Requires Subscription PDF (USD 30)

• Simulation Study of Tapered Shape FinFET

  A. Shrivastava, S. Singh, A. Acharya, G Musalgaonkar

  21-31

  • Requires Subscription PDF (USD 30)

• Switched Capacitor-based RC Filter

  jinal A prajapti, Mehul L Patel

  32-40

  • Requires Subscription PDF (USD 30)

• Cluster Based Sleep Transistor Approach for Low Power 6T SRAM Cell

  P. Raikwal, V. Neema, A. Verma

  41-48

  • Requires Subscription PDF (USD 30)

• Design of Single Bitline Novel 5T SRAM Cell to Reduce The Power Dissipation Using Cadence

  J. K. Arya, A. Raman

  49-54

  • Requires Subscription PDF (USD 30)

• Implementation of Edge Detection Algorithm on FPGA using Hardware Software Co-simulation

  akash mecwan, bhupendra fataniya, dhaval shah

  55-61

  • Requires Subscription PDF (USD 30)

• Modeling of Voltage Buffer and Memristor Voltage Buffer Using 180 nm Technology

  Herman Al Ayubi, navaid Z. rizvi, piyush K. Mishra

  62-72

  • Requires Subscription PDF (USD 30)

• Review Paper on Static and Dynamic Power Dissipation of Novel CMOS SRAM Cell

  Jitendra Krishna Arya, Ashish Raman

  73-77

  • Requires Subscription PDF (USD 30)

• GDI Logic Implementation of Variable Sized CSLA Architectures Using 45 nm SOI Technology

  jubal saji, shoaib kamal

  78-88

  • Requires Subscription PDF (USD 30)

• A Differentiator Based on Second Generation Current Controlled Conveyor

  A. Kumar, R. Pandey

  89-95

  • Requires Subscription PDF (USD 30)