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A Review for Power Optimization in MOS Devices using Different Logic Styles

M. Hulkey, H. Upadhyay, K. Sujatha

Abstract


This paper presents power optimization in MOS devices by using different logic styles which is helpful for increasing high speed application. The simulation process can be done in different CMOS technologies and performance parameter of power is compared for different logic styles. Full adder and ripple carry adder are mostly used to define different logics to optimize the power. Constant logic style provides the low power and different logic style is also helpful for minimization of power to a great extent as compared to constant delay logic style.

 

Keywords: CMOS, adder, constant delay, power consumption, full adder, ripple carry adder, high performance


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