32-bit Single Cycle MIPS RISC Processor

Abstract

In this report, I have written a Verilog HDL code for the MIPS 32-bit single-cycle RISC Processor and simulate the same. I have derived the result in four points first in terms of resource utilization, an RTL design view, TTL design view, and perform simulation on emulator using machine code. The topics I have cover the report are how to define instruction set for RISC architecture? Designing of various digital components module like adder, shift register, ALU, Memory unit, MUX and how to combine this all to build an CPU? We will see types of instruction set and Computer architecture for single Cycle process.