FDTD-based Time Domain Analysis of CMOS Gate Driven Interconnects

Abstract

Accurate time domain analysis of CMOS gate driven interconnects is important for the design and analysis of high performance VLSI systems. Conventionally, CMOS driver is approximated as a constant resistance instead of non-linear and time-varying MOS resistance, which causes inaccurate modeling of CMOS driver. This paper presents a new method for FDTD-based transient analysis of CMOS gate driven interconnect line using a generalized model. The generalized model of CMOS inverter includes non-linear effects such as carrier’s velocity saturation effect of short channel devices, while distributed interconnect RLC model is analyzed using conventional FDTD with second order accuracy. The simulation results of the proposed method are in good agreement with LTspice results and considerable savings in CPU computation time is observed.