Improvement of Design Issues in FinFET based Design Techniques for XOR and XNOR Circuits at 45 nm Technology

Abstract

The scaling of conventional CMOS circuit inclines to the short channel effect due to leakage current increase in the circuit. To minimize the short channel effect, FINFET can be used in place of conventional CMOS circuits. This paper demonstrates comparative performance study of high speed, low power and low voltage on XOR and XNOR digital circuit.  This paper assesses and compares the performance of   XOR and XNOR logic circuits. This comparison is based on analysis of various design technique for XOR and XNOR logic circuits. The performances of XOR and XNOR circuits are based on CADANCE VIRTUOSO tool at voltage supply 0.6 voltages and the temperature is 26⁰C and all the simulation results have been generated by Cadence SPECTRE simulator at 45 nm technology. The XOR and XNOR circuits with pass transistor, inverter based design, transmission gate and with feedback transistors designs are desirable for arithmetic circuits.  Simulation results reveal low power, delay, power, delay product (PDP), average dynamic power consumption and energy delay product (EDP).