Designing of Low Power Charge Pump Circuit with Minimum Current Mismatch for High Speed PLL Applications

Abstract

Charge pump (CP) is one of the necessary block of phase locked circuit (PLL). This paper presents the new design of CP circuit, i.e., cascode current source biased transmission gate based CP circuit. Cascode current mirror, transmission gate switches and unity gain follower amplifier are combined to design the CP circuit in 65 nm technology. The reference current is used to bias the switches of CP circuit so that current mismatch problem in the proposed circuit will be removed. The proposed design is simulated using cadence spectre tool. Simulation results describes that the proposed circuit has a wide output range of 0.44–0.85 V. The supply voltage for proposed design is 1.1 V. The design has low power consumption of nearly 55 µw. Maximum current mismatch in the proposed circuit is nearly 10%. The design has a moderate phase noise, i.e., approximately -105 dBc/Hz at 200 MHz. The performance of the proposed design is compared with existing design available in the literature. Keywords: phase locked loop (PLL), charge pump (CP), charge injection, clock feed through, current matching