Performance Analysis of 1-Bit Full Adder using GDI and CMOS Logic

Abstract

The adder is one of the most essential part in math processor, multiplier, and in various scientific applications. Full adder plays important role in multiplier architecture. In this paper a 1-bit full adder using GDI and CMOS logic has been implemented and comparative analysis has been done. The less delay and low power consumption is achieved for this implementation. This paper presents comparison of number of transistors have been used for both logic styles are shown in table. The design of 1-bit full adder has been implemented in TANNER EDA version 15 tool using BPTM 45nm CMOS process technology. Keywords: Full Adder, GDI logic, CMOS technique, 45 nm technology, TANNER EDA, simulation result