Delay Analysis for VLSI Interconnect’s Circuits

Abstract

This research work has been comprised of three parts. The first part deals with the implementation and estimation for the delay of an inverter and study of the influence of the delay variations with the increased size of the inverter. In this modern era of VLSI integrated circuits, interconnect’s delay majorly influences the device delay. The second phase of the work emphasizes on the realization of the interconnect delay and interprets the change in interconnect delay with the change in the length of the interconnect. It has been observed that the interconnect delay varies quadratically with respect to its length. This causes the interconnect delay to become non-acceptable to be used as global interconnects, as they are quite large in length. The delay can further be reduced (linearized) by inserting inverters or buffer circuit in between the interconnectnet work. The next part is, to realize delay for the interconnect having buffer circuit. This, results in achieving the optimized segment length of the interconnect with minimum delay. Keywords: INVX4, INVX8, INVX16, INVX32, PTM