Designing and Testing of various types of SRAM topologies with 90nm Technology

Abstract

VLSI technology provides a way for designing compact devices which are useful to human for leading their day to day, the advancement in the technology provides high speed and power consuming appliances. In this category, intend to design an application with high data rate and low power, memory efficient device and Static Random-Access Memory (SRAM) is structured. Improvement in the technology comprises of scaling down the design process and impact in the noise margin and make it minimum in the proposed SRAM cells. Due to the shrinking of SRAM cell it leads to a power leakage in the circuit which makes losses in the data transition. To overcome this issue, this article intended to concentrate on the power dissipation in the SRAM during transition of data from one state to another state. The objective is solved for the 6T, 7T, 8T and 9T by designing the structure with dual- threshold-voltage at the SRAM designing process. By the proper implementation the power dissipation and overall delay in transition in the cells are analyzed and evaluated. This is implemented in 90nm Generic Process Design Kit (GPDK) using tanner tool Schematic Composer and the Specter as the simulator.