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FPGA Implementation of LDPC Codes

Sachit Gupta, Richa ., Adesh Kumar



Low Density Parity Check (LDPC) are the linear error correction codes for amendment of mistakes, a technique of transmitting the messages over the noisy channel. With lieu- Shannon’s controlled implementation and typically parallel execution of plan, low-density parity check codes are mainly executed at enquire and well-designed area of applications. Bipartite graph is used for development of LDPC codes. LDPC being limit stirring in the direction of codes which means its actual building exists that enables outer edge to be closely intended for symmetry of a channel with no memory. FPGA or Field Programmable Gate Array is based on configurable logic block (CLB) and is a semiconductor gadget that is associated by virtue of programmable interconnects. FPGAs are highly robust and can be created or designed as per the application or usefulness prerequisite of application. This research paper presents adaptable and more compatible LDPC decoder in change for other general LDPC decoder. This decoder has a completely adaptable LDPC plan in FPGA, which supports distinct codes and rate of information. The design is implemented in Xilinx ISE 14.2 software using VHDL programming and synthesized on SPARTAN 3E FPGA.

Keywords: Sparse bipartite graph, threshold, Shannon limit, Very High Speed Integrated Circuit Hardware Description Language (VHDL)

Cite this Article

Sachit Gupta, Richa, Adesh Kumar. FPGA Implementation of LDPC Codes. Journal of Telecommunication, Switching Systems and Networks. 2018; 5(1): 21–28p.

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