GDI Logic Implementation of Variable Sized CSLA Architectures Using 45 nm SOI Technology

Abstract

Carry select adder (CSLA) is an efficient adder used in modern processors. But, the CMOS logic implementation at the transistor level makes it complex. The use of smaller transistor size has shrunk the overall design but the transistor count was retained. Hence, in this paper the transistor level implementation of variable sized CSLA architecture is done using gate diffusion input (GDI) logic. This implementation drastically simplifies the CSLA in terms of the transistor count which also helps in reducing the power. The variable sized CSLA and the modified variable sized CSLA using binary to excess-1 converter (BEC) are designed using 45 nm silicon-on-insulator (SOI) transistors. A comparative analysis of both GDI and CMOS logic designs are carried out based on the transistor count and power, where the SOI based GDI logic circuits have an upper hand. Further, the variable CSLA using BEC in SOI based GDI logic outperforms the conventional CSLA architecture.

Keywords: Binary to excess-1 converter (BEC), carry select adder (CSLA), gate diffusion input (GDI), silicon-on-insulator (SOI), 45 nm technology