Area Efficient Layout Design of Two Bit Magnitude Comparator Using Novel Strategy

Abstract

The development of digital circuits, digital signal processors and other data processing integrated circuits, comparators are challenged by large area consumption. Comparator is most basic and fundamental component that performs comparison operation. This paper proposes a new approach to design an area efficient two bit magnitude comparator. Comparison is done on the grounds of area and power consumed between circuit designed by novel strategy and preexisting CMOS technique. The novel technique described in this paper is found to be effective and efficient to reduce the chip area.

Keywords: Two bit, magnitude comparator, layout design, chip area, power consumption