Vol. 6 No. 3 (2016)

Articles

• Area Efficient Layout Design of Two Bit Magnitude Comparator Using Novel Strategy

  shashank gautam, pramod sharma

  1-6

  • Requires Subscription PDF (USD 30)

• Design of Booth Encoded Multi-Modulus {2n-1, 2n, 2n+1} RNS Multiplier

  saguna goel, sakshi bajaj, amanpreet kaur

  7-14

  • Requires Subscription PDF (USD 30)

• Design of FPGA Based ALU Using Reversible Logic Gates

  vishal A Wankhede, ramprasad M gawande

  15-21

  • Requires Subscription PDF (USD 30)

• Linearity Analysis of Traditional Single and Double Balanced Down Conversion Mixers

  akash I mewan, N M Devashrayee

  22-27

  • Requires Subscription PDF (USD 30)

• Development of System for Speech Enhancement using Combinational Adaptive LMS on Reconfigurable Platform

  pradeep C bhaskar, prachi S gosavi

  28-34

  • Requires Subscription PDF (USD 30)

• Design of High-Speed and Low-Power Carry Skip Adder

  gutlapalli venkatrao, motkuri krishna

  35-44

  • Requires Subscription PDF (USD 30)

• A Unified Ultra-Low Power Architecture of Probabilistic Adder Based on GDI Technique

  B S Patro, srinibasa padhy, monica swain, J K Das

  45-55

  • Requires Subscription PDF (USD 30)

• Survey of System-on-Chip Modular Test Approach

  harpreet vohra, amardeep singh

  56-70

  • Requires Subscription PDF (USD 30)

• Design of Low Power Resistor Less Flash ADC for UWB Receiver Applications

  ankush chunn, rakesh kumar sareen

  71-87

  • Requires Subscription PDF (USD 30)

• VHDL Implementation of Network-on-Chip Router using Round Robin Arbiter

  minakshi m wanjari, pankaj agrawal, ravindra kashirsagar

  88-93

  • Requires Subscription PDF (USD 30)