Design of Low Power Resistor Less Flash ADC for UWB Receiver Applications

Authors

  • ankush chunn Department of VLSI Design, Dr. B. R. Ambedkar National Institute of Technology, Jalandhar, Punjab, India
  • rakesh kumar sareen

DOI:

https://doi.org/10.37591/jovdtt.v6i3.3007

Abstract

In this paper, two designs of flash analog to digital converters (ADCs) based on threshold inverter quantization (TIQ) technique are presented. The parallel threshold inverter quantization (PTIQ) flash ADC exploits the advantage of reduction in capacitance and power consumption if the transistors are placed in parallel. Another design called low voltage tunable body bias (LVTBB) PTIQ ADC operates at near threshold voltage level to minimize the power consumption. The PTIQ and LVTBB ADC designs attain figure of merit of 0.09625 pico Joule/conversion (pJ/conv) and 0.06 pJ/conv respectively which is comparable to the existing state of art ADCs.

 

Keywords: ADC, TIQ, PTIQ, LVTBB, threshold voltage, power consumption

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Published

2019-08-09

Issue

Vol. 6 No. 3 (2016)

Section

Articles

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