VHDL Implementation of Network-on-Chip Router using Round Robin Arbiter

Abstract

As the technology progresses, a large number of devices can be incorporated into a single chip. So, the communication between these devices becomes critical. The network-on-chip (NoC) is a technology used for such communication and overcomes the constraints of traditional bus-based system-on-chip (SoC). Router is the backbone of NoC and determines the performance to a great extent. This paper focuses on the implementation of five port virtual channel router which is considered as promising router architecture for NoC. The major building blocks of router are virtual channel buffer architecture, fairness arbiter, i.e. RRA and a crossbar switch. An arbiter employs a scheduling algorithm which is used to decide which one of several requests would be serviced. The round robin arbiter is based on the assignment of a fixed time slot per requester. The source code is written in VHDL. The proposed router is synthesized and simulated in Xilinx ISE Design Suite 13.1.

Keywords: Network-on-chip (NoC), system-on-chip (SoC), intellectual property (IP), processing element (PE), network interface (NI), virtual channel (VC), round robin arbiter (RRA)