Design of Decoder Using Domino Logic Circuit for VLSI

Abstract

Dissipation of power from a circuit is the major issue in the design of any VLSI circuit, which decreases the life span of a device/system. NMOS and PMOS circuits are very slow while switching the state from low to high. The speed of the circuit can be increased by decreasing resistance. This process in turn increases the static power dissipation. So, because of these disadvantages, CMOS circuits are used in many applications. For any CMOS circuit, the dissipation of power can be both static and dynamic. Dynamic dissipation in CMOS circuits occurs because of the switching of states. However, the static power dissipation is negligible in the circuit. Circuits designed using the domino model are used in various applications, like full adders, multiplexers, in memory as address selectors, comparators, and arithmetic circuits. There are different issues in domino logic circuits, namely power consumption, speed, and power delay product. A model is designed based on various approaches to solve these issues.