Implementation of Different Low Power Techniques on CMOS Inverter and NAND Circuits

Authors

  • Karishma Yadav The NorthCap University, Gurgaon, India
  • Vandana Khanna The NorthCap University, Gurgaon, India
  • Gaurav Shingwani The NorthCap University, Gurgaon, India
  • Ishita Ishita The NorthCap University, Gurgaon, India

DOI:

https://doi.org/10.37591/jovdtt.v9i1.1449

Abstract

The growth in technology has increased the usage of additional components on a single chip. This increased number of components on a single chip increases the significant amount of power dissipation and this causes the major challenge for the today’s circuit designers. There are several techniques in VLSI field which help to reduce power dissipations. This paper has analytical analysis of different low power techniques on CMOS inverter and NAND circuits; significant amount of power reduction in these circuits designed in 180 nm have been achieved.

Keywords: Dynamic power, static power, leakage power, power dissipation, LECTOR

Cite this Article

Karishma Yadav, Vandana Khanna, Gaurav Shingwani, et al. Implementation of Different Low Power Techniques on CMOS Inverter and NAND Circuits. Journal of VLSI Design Tools & Technology. 2019; 9(1): 38–43p.


Author Biographies

  • Karishma Yadav, The NorthCap University, Gurgaon, India
    M.Tech student, department of EECE.
  • Vandana Khanna, The NorthCap University, Gurgaon, India
    Faculty, Department of EECE.
  • Gaurav Shingwani, The NorthCap University, Gurgaon, India
    Student, department of EECE.
  • Ishita Ishita, The NorthCap University, Gurgaon, India
    Student, department of EECE

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Published

2019-04-20

Issue

Vol. 9 No. 1 (2019)

Section

Articles

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