Power Analysis Comparison of Gated Diode Dram Cell Design on 32 nm Technology

Authors

  • Prateek Asthana Department of Electronics and Communication, JSS Academy of Technical Education, Noida, U.P., India
  • Sangeeta Mangesh Department of Electronics and Communication, JSS Academy of Technical Education, Noida, U.P., India

DOI:

https://doi.org/10.37591/jovdtt.v5i1.1579

Abstract

In this paper power consumption of Gated diode DRAM (Dynamic Random Access Memory) cells are carried out. This analysis is carried out on 32 nm scale. The DRAM cell used here are 3T1D and 2T1D DRAM cell. Static, total average and transient power for both types of cells are simulated in order to have a comparison of their performance on the same technology. A comparative study of different types of power consumed for both types of gated DRAM cell design has been carried out. These circuits are analyzed, simulated and their power calculations are carried out on HSPICE.

Keywords: Low power, HSPICE, DRAM, 3T1D DRAM, 2T1D DRAM, memory design

Cite this Article
Prateek Asthana, Sangeeta Mangesh. Power Analysis Comparison of Gated Diode Dram Cell Design on 32 nm Technology. Journal of VLSI Design Tools & Technology (JoVDTT). 2015; 5(1): 19-23


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Published

2019-02-13

Issue

Vol. 5 No. 1 (2015)

Section

Articles

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