Hybrid CMOS-SET Inverter Design for Improved Performance using Tied Body-backgate Technique

Authors

  • Prashant Gupta Department of Electronics and Communication Engineering, Birla Institute of Technology (Deemed University), Mesra, Ranchi, Jharkhand, India
  • Shashank Kumar Ranu Department of Electronics and Communication Engineering, Birla Institute of Technology (Deemed University), Mesra, Ranchi, Jharkhand, India
  • Manish Kumar Pandey Department of Electronics and Communication Engineering, Birla Institute of Technology (Deemed University), Mesra, Ranchi, Jharkhand, India
  • Aminul Islam Department of Electronics and Communication Engineering, Birla Institute of Technology (Deemed University), Mesra, Ranchi, Jharkhand, India

DOI:

https://doi.org/10.37591/jovdtt.v5i1.1580

Abstract

Single-electron transistors (SETs) are an attractive candidate for future functional elements in LSIs, because of their low-power consumption and small size. Integration of current CMOS technology with the emerging SET devices is an effective approach for improving density of integration in VLSI chips and ensuring ultra low power dissipation along with the advantages of CMOS technology like high gain, current drive, speed and matured fabrication technology. This paper investigates hybrid CMOS-SET-based inverter for its functionality and performance. It then proposes and analyzes the effect of tied body-backgate technique on design metrics (propagation delay and power-delay product (PDP)). The proposed technique offers 2.38× and 4.09× improvement in propagation delay and power-delay product, respectively.

Keywords: CMOS, single electron transistors, propagation delay, power delay product

Cite this Article:
Gupta P, Ranu SK, Pandey MK, Islam A. Hybrid CMOS-SET Inverter Design for Improved Performance Using Tied Body-Backgate Technique. Journal of VLSI Design Tools and Technology (JoVDTT). 2015; 5(1): 24–29p.

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Published

2019-02-13

Issue

Vol. 5 No. 1 (2015)

Section

Articles

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